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Opportunities



Senior Validation Engineer

in Engineering and Technical

Location

Kanata, Ontario

Job Description

  • Position will require environment development for complex system functional verification.
  • Debug both functional and environmental errors in the RTL using simulation and debugging tools.
  • An in-depth understanding of verification architectures and HDL/logical design are required.
  • Develop automated regression infrastructure setup for functional verification of high complexity ASIC and SoC designs
  • Develop and use constrained-random transactors to validate functionality of system designs
  • Debug regression fails at the RTL and gate levels

COMPENSATION: Salary, Benefits, Vacation                                            

EMPLOYMENT TYPE: Permanent 

Required Skills

  • 7-10 years of hands-on verification experience
  • Direct experience with OVM/UVM or VMM simulation environments
  • Knowledge of computer and peripheral architectures
  • Knowledge of networking and processor protocols – Ethernet, PCIe, Interlaken, SATA, USB, DDR
  • Verilog, SystemVerilog, Specman e Perl, C/C++
  • Directed and constrained-random functional test environment development and usage
  • Experience with functional/power/performance verification using simulation and emulation environments
  • Creation of test plans for complex IPs
  • Development of test benches in OVM/UVM/VMM, SystemVerilog and/or C++
  • Application of applying pseudo-random test generators
  • Development of System Verilog/C/assembly tests
  • Coverage analysis techniques

Contact

paruja@theaimgroup.com

Expiry Date

Friday, October 6, 2017

Submit an Application